Area-oriented technology mapping for LUT-based logic blocks
International Journal of Applied Mathematics and Computer Science, Tome 27 (2017) no. 1, p. 207.

Voir la notice de l'article dans European Digital Mathematics Library

One of the main aspects of logic synthesis dedicated to FPGA is the problem of technology mapping, which is directly associated with the logic decomposition technique. This paper focuses on using configurable properties of CLBs in the process of logic decomposition and technology mapping. A novel theory and a set of efficient techniques for logic decomposition based on a BDD are proposed. The paper shows that logic optimization can be efficiently carried out by using multiple decomposition. The essence of the proposed synthesis method is multiple cutting of a BDD. A new diagram form called an SMTBDD is proposed. Moreover, techniques that allow finding the best technology mapping oriented to configurability of CLBs are presented. In the experimental section, the presented method (MultiDec) is compared with academic and commercial tools. The experimental results show that the proposed technology mapping strategy leads to good results in terms of the number of CLBs.
Mots-clés : SMTBDD, FPGA, synthesis, decomposition 
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     author = {Marcin Kubica and Dariusz Kania},
     title = {Area-oriented technology mapping for {LUT-based} logic blocks},
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     pages = {207},
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     volume = {27},
     number = {1},
     year = {2017},
     language = {en},
     url = {https://geodesic-test.mathdoc.fr/item/IJAMCS_2017__27_1_288101/}
}
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Marcin Kubica; Dariusz Kania. Area-oriented technology mapping for LUT-based logic blocks. International Journal of Applied Mathematics and Computer Science, Tome 27 (2017) no. 1, p. 207. https://geodesic-test.mathdoc.fr/item/IJAMCS_2017__27_1_288101/